Logic Synthesis and Verification, Fall 2020

Graduate course, Graduate Institute of Electronics Engineering, National Taiwan University, 2020

This lecture is instructed by Prof. Jie-Hong R. Jiang. As a teaching assistant, I am in charge of the programming assignments, where students have to practice using a synthesis and verification tool ABC. I created a GitHub repository for students to learn modern approaches of software development, including version control and continuous integration. Students have to fork the repository and submit their solutions as pull requests. Their solutions will be tested automatically with GitHub Actions. It was our first time to implement this workflow for programming assignments, and most students gave positive feedbacks. I also wrote a tutorial for students to get their hands on ABC.